The IBM ESA/390 architecture requires some very precise implemelitation requirements regarding the STORE THEN OR SYSTEM MASK (STOSM) and STORE THEN AND SYSTEM MASK (STNSM) instructions. These instruction modifies the system mask field in the PSW.
In previous IBM S/390 processor designs, this problem was solved by either executing the instruction in microcode/millicode or by unconditionally serializing the processor after execution of the STOSM or STNSM instructions. By serializing the processor, we mean discarding all instructions that have been pre-fetched or decoded but not executed to completion and restarting instruction fetching again. This would allow time for the asynchronous interrupt logic to correctly determine if an I/O or external interrupt is really present based on the updated copy of the bits in the PSW. However, this serialization processor wastes cycles and reduces processor performance. Another solution would be to artificially lengthen the execution time of the STOSM and STNSM instructions to allow the asynchronous interrupt logic to process any interrupts based on the updated PSW bits. But again, this reduces processor performance. The IBM ESA/9000 series as disclosed in U.S. Pat. No. 5,345,567 used a method to minimize serializations following STOSM/STNSM. However, since it had a method of nullifying an instruction at anytime during its execution, it had an easy general mechanism for handling STOSM with full instruction overlap. In other processor designs, however, it is not possible to nullify an instruction after its execution has begun. Therefore, without this invention the STOSM and STNSM instructions could not be executed with full instruction overlap, so a need arises to maintain the system architecture stability yet allow better timing in our new machines.
Consistent with the disclosure in U.S. Pat. No. 5,345,567, issued Sep. 6, 1994 and entitled "System and method for modifying program status word, system mask, system access key, and address space code with overlap enabled" by Hayen et al, in an S/390 CPU, the STORE THEN OR SYSTEM MASK (STOSM) and STORE THEN AND SYSTEM MASK (STNSM) instructions are used to modify bits 0:7 of the PSW, called the System Mask. STOSM can only turn on bits in the System Mask and STNSM can only turn bits off. They are commonly used to quickly enable or disable I/O or External Interrupts (bits 6:7 of the PSW). Obviously since bits 0:5 can also be modified by these instructions, an implementation must handle this usage, although it is not nearly as performance critical as changes to bits 6:7.
The ESA/390 architecture requires some very precise implementation requirements. Suppose, for example. an External Interrupt is pending but bit 7 of the PSW is 0. Now suppose the processor executes a STOSM instruction that sets bit 7 to 1. The ESA/390 architecture requires the External Interrupt to be taken immediately after executing the STOSM instruction and before executing the next sequential instruction. This makes it difficult to implement a STOSM instruction efficiently.
Similarly, suppose an External Interrupt has just become pending during the execution of a STNSM instruction. Now suppose this STNSM instruction sets bit 7 of the PSW to 0. The ESA/390 architecture requires that no External Interrupt should be presented after the STNSM instruction has turned off bit 7 of the PSW.
There are also complications in the START INTERPRETIVE EXECUTION (SIE) environment related to the STOSM instruction. If the XPIE bits in the SIE state descriptor indicate a SIE intervention check needs to be performed when a STOSM instruction turns on bits 6 or 7 in the PSW, this must be done immediately after the STOSM instruction is completed. This intervention check is typically too complex to perform in hardwired logic, so it is normally performed by microcode or millicode as it is in the processor described in the preferred embodiment of this invention. The interrupt to invoke this microcode/millicode routine takes several cycles to occur, so other instructions must be blocked from occurring until it is determined if a SIE intervention check needs to be performed.